The present invention relates in general to electronic systems and components, and is particularly directed to a new and improved circuit architecture for providing overvoltage protection for a bidirectional transmission gate, particularly one formed of complementary polarity field effect transistors.
FIG. 1 diagrammatically illustrates the basic circuit architecture of a conventional complementary polarity FET-based bidirectional transmission gate 10 commonly employed in a variety of electronic circuits and systems for selectively switching analog signals between a first port 11 and a second port 12. While bidirectional switching allows either port to be employed as an input or an output, for purposes of avoiding confusion in the use of dual terms for both ports, throughout the following present description, port 11 will be designated as an input port IN and port 12 will be designated as an output port OUT.
The complementary polarity FET-configured transmission gate 10 of FIG. 1 contains a first, N-channel MOSFET (or NMOS) device 20 (a cross-section of which is diagrammatically illustrated in FIG. 2) having its (N+) source 21 coupled to input port 11 and its (N+) drain 22 coupled to output port 12. The P-type body 24 of NMOS device 20 is coupled to its source 21 (by way of an external connection not show in FIG. 2), and its gate 23 is coupled to a control terminal C. The body-source connection may be represented as a parasitic base connection of a parasitic NPN transistor, shown in broken lines 30 in the device cross-section of FIG. 2, and having respective parasitic emitter-base and base-collector pn junctions 31 and 32 of the NMOS device schematic shown in FIG. 3. To place the NMOS device 20 in the OFF or non-conducting condition the control terminal C is coupled to receive a low logic level switching control voltage such as one corresponding to a negative supply voltage; to place NMOS device 20 in the ON or conducting condition, the control terminal C is coupled to receive a high logic level switching control voltage, such as a positive supply voltage.
The transmission gate 10 of FIG. 1 further contains a second, P-channel MOSFET (or PMOS) device 40 (a cross-section of which is diagrammatically illustrated in FIG. 4) having its (P+) source 41 coupled to input port 11 and its (P+) drain 42 coupled to output port 12. The N-type body 44 of PMOS device 40 is coupled to its source 41 (as by way of an external connection not shown in FIG. 4), and its gate 43 is coupled to a control terminal CBAR. The body-source connection can be represented as a parasitic base connection of a parasitic PNP transistor, shown in broken lines 50 in the device cross-section of FIG. 4, and having respective parasitic emitter-base and base-collector pn junctions 51 and 52 of the PMOS device schematic shown in FIG. 5.
To place the PMOS device 40 is the OFF or non-conducting condition, its control terminal CBAR is coupled to receive a high logic level switching control voltage such as one corresponding to a positive supply voltage. To place PMOS device 40 is the ON or conducting condition, its control terminal CBAR is coupled to receive a low logic level switching control voltage, such as a negative supply voltage.
In operation, NMOS device 20 may have a threshold voltage VNMOSth=+1V, while PMOS device 40 may have a threshold voltage VPMOSth=xe2x88x921V, with a supply voltage range of +/xe2x88x9215 volts. For an input voltage Vin of +10v applied to input port 11, and a ground or zero potential coupled to the output port 12, as diagrammatically illustrated in FIG. 6, NMOS device 20 has a Vgs20=xe2x88x9225V (xe2x88x9225V less than 1V), while PMOS device 40 has a Vgs40=+5V (+5V greater than xe2x88x921V). As a result, each of NMOS device 20 and PMOS device 40 is turned OFF. Namely, the transmission gate 10 can be maintained. in the OFF condition as long as the input voltage falls within the supply voltage range.
On the other hand, for an excessively positive or overvoltage input voltage Vin of +20 v applied to input port 11, and a ground or zero (0) potential coupled to the output port 12, as shown diagrammatically in FIG. 7, NMOS device 20 has a Vgs20=xe2x88x9235V (xe2x88x9235V less than 1V), so that NMOS device 20 is apparently turned OFF. However, PMOS device 40 has a Vgs40=xe2x88x925V (which is less than xe2x88x921V), so that PMOS device 40 is undesirably turned ON and provides substantial current flow therethrough. Moreover, even though NMOS device 20 is in the OFF state, the +20 volt applied to the input port 11 is sufficient to forward bias its parasitic base-collector pn junction 32 and provide an additional current leakage path through NMOS device 20 between ports 11 and 12.
Similarly, for an excessively negative or overvoltage input voltage Vin of xe2x88x9220 v applied to input port 11, and a ground or zero (0) potential coupled to the output port 12, shown diagrammatically in FIG. 8, the NMOS device 20 has a Vgs20=+5V ( greater than +1V), so that the NMOS device 20 is undesirably turned ON, while PMOS device 40 has a Vgs40=+35V (which is greater than xe2x88x921V), so that PMOS device 40 is turned OFF. Although the PMOS device 40 is ostensibly in the OFF state, the xe2x88x9220 volt applied to the input port 11 is sufficient to forward bias its parasitic base-collector pn junction 52 and thereby provide an additional current leakage path through PMOS device 40 between ports 11 and 12. Thus, the transmission gate 10 fails to remain OFF for an input voltage outside the supply voltage range (regardless of polarity).
FIG. 9 diagrammatically illustrates a modification that may be incorporated into each of the complementary polarity halves of the transmission gate described above, to incorporate a xe2x80x98blockingxe2x80x99 diode coupled between the body and a respective supply rail, as well as a complementary MOSFET inverter coupled in circuit between the body and an opposite polarity supply rail. In order to reduce the complexity of the drawings and facilitate the present description, only the PMOS device 40 of the transmission gate will be described. It is to be understood, however, that the description applies equally to the complementary NMOS device 20 for a change in polarity of the parameters of the components and applied voltages.
More particularly, in the modified circuit of FIG. 9, a xe2x80x98blockingxe2x80x99 diode 45 is installed between the body 44 and a (+15V) positive supply terminal 46. In addition, a complementary MOSFET inverter 60 comprised of a PMOS transistor 61 and an NMOS transistor 62, is coupled in circuit between body 44 and a (xe2x88x9215V) negative supply terminal 47. The gate 43 of PMOS transistor 40 is coupled to the common drain connections of PMOS device 61 and NMOS device 62, and the common gates of devices 61 and 62 are coupled to a control terminal (to which a logic low input voltage (xe2x88x9215V) is coupled for an OFF condition of the transmission gate). In terms of a practical implementation, an MOS device may be coupled between the diode 45 and the body 44 of the PMOS device 40 for the purpose of isolating the body 44 from the positive supply rail, when the transmission gate is turned ON, in order to connect the transmission gate""s NMOS and PMOS bodies together, to provide a flatter on-resistance vs. input voltage caused by the constant body source-voltage allowed by the configuration shown.
For the above parameters, as long as the input voltage remains within the supply voltage range (+/xe2x88x9215V), the transmission gate can be controllably maintained in the OFF condition. (As shown in FIG. 10, the parasitic PNP transistor 50 will also remain OFF, with both emitter-base and base-collector PN junctions being reverse-biased, so that the parasitic transistor remains turned OFF.) For a voltage outside this range applied to the input port, the two complementary transmission gate transistors remain off.
For the case of a +20V overvoltage applied to input port 11, as shown in FIG. 11, the PMOS device""s blocking diode 45 is reverse-biased, which allows the node 44 to exceed the supply voltage (+15V). The body potential increases toward the +20V input voltage minus the internal diode drop (e.g., 0.6V) of the PMOS pn junction 51 which is forward-biased. With PMOS 61 device of inverter 60 being turned ON, the potential at the gate 43 of PMOS transistor 40 will rise toward the higher body potential (20 vxe2x88x920.6 v=19.4 v). This places PMOS gate in an OFF condition (or approximately sub-threshold region), as the Vgs40 is not sufficient to turn device 40 ON. The parasitic PNP bipolar transistor 50 is not turned on, since this transistor""s base (the body 44 of the PMOS device 40) is not provided a major current path, so that it does not fully turn on (does not saturate).
On the other hand, where a +20V overvoltage is applied to the output port 12, as shown in FIG. 12, the PMOS device""s blocking diode 45 is reverse-biased, through the forward-biased pn junction 52, which allows the potential of the body 44 to rise to within a diode drop of the overvoltage potential, thus increasing the gate voltage through the turned-on PMOS 61 device of inverter 60 to the higher body potential (20Vxe2x88x920.6V=19.4V). This places the PMOS device 40 in the OFF state. However, a relatively large Vds (drain-source voltage) is thereby imparted to the NMOS device 62 within the inverter 60, causing a significant flow of leakage current shown by broken lined arrow 65.
This increased leakage current, in turn, increases the ohmic voltage lossesxe2x80x94causing a larger Vgs and also allowing more parasitic PNP base current to flow than if the leakage current did not exist or is of a smaller amount. This current leakage problem is aggravated by the use of a larger transmission gate transistor to provide a low on-resistance requirement. As the size of the transmission gate transistor is increased, more leakage current will flow for the same value of Vgs. This causes the overvoltage protection rating for a given switch leakage to be lower than if the problem did not exist.
In accordance with the present invention, this reduced overvoltage protection rating problem is successfully remedied by incorporating at least one auxiliary xe2x80x98clampingxe2x80x99 MOS transistor in circuit with the overvoltage path and the gate terminal of the transmission gate MOS transistor. Pursuant to a first embodiment of the invention, a single auxiliary clamping MOS device may be coupled in circuit with the input path as long as there is a defined output and only the input is subject to the possibility of an overvoltage condition. The clamping MOS device-modified circuit functions in substantially the same manner as the circuit of FIG. 11, described above, with the following exception.
When the voltage applied to the input port exceeds the supply voltage by the MOS gate threshold, the auxiliary clamping MOS transistor is turned on, thereby xe2x80x98pullingxe2x80x99 the voltage applied to the gate of the transmission gate FET very close to the applied overvoltage level by a voltage differential that is less than a diode drop. This reduction in Vgs of the transmission gate MOSFET reduces its source-to-drain current, as the MOS device now operates deeper in its sub-threshold region, thereby increasing the overvoltage rating for the same leakage current specification.
The inability of the single clamping device-based embodiment to provide overvoltage protection for an overvoltage applied to either the input port or the output port of the transmission gate is successfully remedied a second embodiment of the invention, in which a clamping MOS device is coupled on either side of the source-drain path of the transmission gate""s MOS device. In addition, rather than coupling the gate of a respective clamping device to the supply voltage terminal as in the first embodiment, the gates of the clamping devices are coupled in circuit with and controlled by associated clamping control MOS devices.
These additional clamping control devices have their source-drain paths coupled between the supply voltage and the gates of the clamping devices; also their gates are coupled to respective ones of the input and output ports. By installing such clamping control devices between the supply rail and the gates of the actual clamping devices on either side of the MOS transmission gate device, only that clamping device installed on the side of the transmission gate encountering the overvoltage condition will be turned on, whereas the clamping device on the opposite side of the transmission gate will be held off (by the blocking action of its associated turned-off clamping control device).
When a respective clamping control transistor is turned on, it causes a voltage that is very close to the supply rail voltage to be applied to the gate of its associated clamping transistor. Since the source of the clamping transistor is coupled to the port to which the overvoltage is applied, the clamping transistor is turned on, providing the intended overvoltage protection. The other clamping control transistor is off, thereby putting a blocking diode in and allowing the other diode to forward bias, thus applying the overvoltage to the gate of the other clamping transistor, keeping it off. At the conclusion of the overvoltage condition, the appropriate clamping control transistor for the non-overvoltage port will turn on the previous, off state (during overvoltage condition), thereby shorting out an associated source-drain diode, causing accumulated charge to be drained off the gate of the clamping transistor, reducing the voltage for normal operation.